ZYNQ PL通过EMIO ETHE1外接PHY由GMII转RGMII：
详见博客：/wangjie36/article/details/107656663
ZYNQ使用AXI_Ethernet编译系统扩展多网口：
详见博客：/editor/html/104765046
一，硬件MIO引脚配置
网口引脚线路等长设计，PL网口的RCK连接到FPGA BANK的MRCC的P脚，其他ETH引脚最好在一个bank内:
时钟域同步时钟输入PL_CLK修改到FPGA BANK的MRCC的P脚，才能作为单端的系统输入时钟。
二，裸机LWIP测试
1，新建LWIP测试例程
2，PS SDK以太网设置
在lwip141的use_axieth_on_zynq中，value选择0，default选择1
修改“platform_config.h”文件，网线连接 PS 端以太网到路由器，可以ping通
3，PL SDK以太网设置
可以通过本地链接的状态查看是多少M的网速。
三，petalinux系统配置：使用内核版本4.9：linux-xlnx-xilinx-v.4
1，petalinux-create --type project --template zynq --name lwip
进入lwip文件夹执行：petalinux-config --get-hw-description your_wapper.hdf ，导入硬件。
Linux Components Selection -> linux-kernel (ext-local-src) -> 填入你的内核路径/home/linux-xlnx-xilinx-v.4
2，记得修改/Downloads/lwip/ax_peta/project-spec/meta-user/recipes-bsp/device-tree/files下的system-user.dtsi为如下：
/include/ "system-conf.dtsi"
/ {
model = "Zynq Development Board";
compatible = "alinx,axi eth", "xlnx,zynq-7000";
usb_phy0: usb_phy@0
{
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
usb-phy = <&usb_phy0>;
};
&sdhci0 {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};
&flash0 {
compatible = "micron,m25p80", "w25q256", "spi-flash";
};
&gem0 {
phy-handle = <ðernet_phy>;
ethernet_phy: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
};
&axi_ethernet_0 {
local-mac-address = [00 0a 35 00 03 22];
phy-handle = <&phy1>;
xlnx,has-mdio = <0x1>;
phy-mode = "rgmii";
mdio {
phy1: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
&axi_ethernet_1 {
local-mac-address = [00 0a 35 00 03 23];
phy-handle = <&phy2>;
xlnx,has-mdio = <0x1>;
phy-mode = "rgmii";
mdio {
phy2: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
3，添加驱动: petalinux-config -c kernel
Device Drivers
-> Network device support
->PHY Device support and infrastructure
-> <*> Micrel PHYs 记得save保存
4，生成启动文件，放入SD卡，ifconfig可以看见eth0,eth1和eth2;
四，debian系统配置
在内核4.14加入驱动：
先source到arm-linux-gnueabihf-的编译环境，然后执行 make menuconfig ARCH=arm
修改system-top.dtsi，要加上如下节点
{
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
axi_dma_0: dma@40400000 {
#dma-cells = <1>;
axistream-connected = <&axi_ethernet_0>;
axistream-control-connected = <&axi_ethernet_0>;
clock-names = "s_axi_lite_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,eth-dma";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 29 4 0 30 4>;
reg = <0x40400000 0x10000>;
xlnx,include-dre ;
};
axi_dma_1: dma@40410000 {
#dma-cells = <1>;
axistream-connected = <&axi_ethernet_1>;
axistream-control-connected = <&axi_ethernet_1>;
clock-names = "s_axi_lite_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,eth-dma";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 33 4 0 34 4>;
reg = <0x40410000 0x10000>;
xlnx,include-dre ;
};
axi_ethernet_0: ethernet@41000000 {
axistream-connected = <&axi_dma_0>;
axistream-control-connected = <&axi_dma_0>;
clock-frequency = <100000000>;
clock-names = "ref_clk";
clocks = <&clkc 0>;
compatible = "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-names = "mac_irq", "interrupt";
interrupt-parent = <&intc>;
interrupts = <0 31 1 0 32 4>;
phy-mode = "rgmii";
reg = <0x41000000 0x40000>;
xlnx = <0x0>;
xlnx,axiliteclkrate = <0x0>;
xlnx,axisclkrate = <0x0>;
xlnx,clockselection = <0x0>;
xlnx,enableasyncsgmii = <0x0>;
xlnx,gt-type = <0x0>;
xlnx,gtinex = <0x0>;
xlnx,gtlocation = <0x0>;
xlnx,gtrefclksrc = <0x0>;
xlnx,include-dre ;
xlnx,instantiatebitslice0 = <0x0>;
xlnx,phy-type = <0x3>;
xlnx,phyaddr = <0x1>;
xlnx,rable = <0x0>;
xlnx,rxcsum = <0x0>;
xlnx,rxlane0-placement = <0x0>;
xlnx,rxlane1-placement = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,rxnibblebitslice0used = <0x0>;
xlnx,tx-in-upper-nibble = <0x1>;
xlnx,txcsum = <0x0>;
xlnx,txlane0-placement = <0x0>;
xlnx,txlane1-placement = <0x0>;
local-mac-address = [00 0a 35 00 00 00];
phy-handle = <&phy0>;
axi_ethernet_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
device_type = "ethernet-phy";
reg = <0x0>;
};
};
};
axi_ethernet_1: ethernet@41040000 {
axistream-connected = <&axi_dma_1>;
axistream-control-connected = <&axi_dma_1>;
clock-frequency = <100000000>;
clock-names = "ref_clk";
clocks = <&clkc 0>;
compatible = "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-names = "mac_irq", "interrupt";
interrupt-parent = <&intc>;
interrupts = <0 35 1 0 36 4>;
phy-mode = "rgmii";
reg = <0x41040000 0x40000>;
xlnx = <0x0>;
xlnx,axiliteclkrate = <0x0>;
xlnx,axisclkrate = <0x0>;
xlnx,clockselection = <0x0>;
xlnx,enableasyncsgmii = <0x0>;
xlnx,gt-type = <0x0>;
xlnx,gtinex = <0x0>;
xlnx,gtlocation = <0x0>;
xlnx,gtrefclksrc = <0x0>;
xlnx,include-dre ;
xlnx,instantiatebitslice0 = <0x0>;
xlnx,phy-type = <0x3>;
xlnx,phyaddr = <0x1>;
xlnx,rable = <0x0>;
xlnx,rxcsum = <0x0>;
xlnx,rxlane0-placement = <0x0>;
xlnx,rxlane1-placement = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,rxnibblebitslice0used = <0x0>;
xlnx,tx-in-upper-nibble = <0x1>;
xlnx,txcsum = <0x0>;
xlnx,txlane0-placement = <0x0>;
xlnx,txlane1-placement = <0x0>;
local-mac-address = [00 0a 35 00 00 01];
phy-handle = <&phy1>;
axi_ethernet_1_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
device_type = "ethernet-phy";
reg = <0x1>;
};
};
};
};
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
};
五，百兆，千兆网线序定义
1，千兆：
MDI
1 2 3 4 5 6 78
DA+DA-DB+DC+DC-DB-DD+DD-
MDI-X
1 2 3 4 5 6 7 8
DB+DB-DA+DD+DD-DA-DC+DC-
2，百兆和十兆：
MDI
12345678
TD+TD-RD+ // RD- //
MDI-X
12345678
RD+RD-TD+ // TD- //
3，UTP的八芯模块(根据TIA/EIA-568布线标准)
T568B(TIA/EIA-568-B):
12345678
白橙橙白绿兰白兰绿白棕棕
T568A(TIA/EIA-568-A):
12345678
白绿绿白橙兰白兰橙白棕棕
10/100/1000BASE-T直通电缆:
T568B-T568B
10/100BASE-T 翻转电缆:
T568B-T568A
1000BASE-T翻转电缆:
T568B - 如下:
12345678
白绿绿白橙 白棕 棕 橙 兰 白兰
六，网口复位：
如果R323焊接0欧电阻，R325断开，则默认为手动复位，可以EMIO或verilog控制电平复位。
如果R323断开，R325焊接0欧电阻，则默认为自动复位，上电自己就完成。
自动复位电路图：
PHY0_P1_TCT后面对应的4个DNP/0欧电阻要焊接上
